Without limiting the scope of the invention, its background is described in connection with semiconductor manufacturing and is best exemplified by methods and processes for fabricating MOS devices. The term “MOS” is used in this application, in its conventional sense, to refer to any insulated-gate-field-effect-transistor, or to integrated circuits (ICs) that include such transistors. The term “N-type” is used in this application to refer to MOS components that reside in regions that have been doped with negatively charged impurities. The term “P-type” is used in this application to refer to MOS components that reside in regions that have been doped with positively charged impurities. The term “ESD” as used in this application refers to electrostatic discharge.
Electrostatic discharge protection circuitry is now an essential component of most modern integrated circuits. IC's contain numerous, extremely small delicate device structures that are very sensitive to electrostatic discharges that occur when the high voltages collect within a circuit and then discharge to ground.
The primary source of electrostatic exposure to ICs is from the human body, and is known as the Human Body Model (HBM) electrostatic discharge source. An electrostatic charge of about 0.6 C (Coulombs) can be induced on a body capacitance of 150 pF (picoFarads), leading to electrostatic potentials of 4 kV (kilovolts) or greater. Any contact by a charged human body with a grounded object, such as the pin of an IC, can result in a discharge for about 100 ns (nanoseconds) with peak currents of several amperes. An electrostatic discharge of this magnitude may result in destruction of the delicate components within the IC.
A second source of electrostatic discharge is from metallic objects, and is known as the Machine Model (MM) electrostatic discharge source. The machine model electrostatic discharge source is characterized by a greater capacitance and lower internal resistance than the human body model electrostatic discharge source. The machine model can result in an electrostatic discharge of significantly higher voltage and duration than the human body model source. As mentioned above, electrostatic discharges of this magnitude have the potential to reduce the service life or destroy delicate components within the IC.
A third electrostatic discharge model is the Charged Device Model (CDM). Unlike the human body model and the machine model sources, the charged device model simulates conditions in which the IC itself becomes charged and discharges to ground. Thus, the electrostatic discharge current flows in the opposite direction in the IC than that of the other modeled sources. Charged device model pulses also have very fast rise times compared to the human body model source.
A significant problem is that if a high voltage is discharged through the pins of an IC package, the discharge can cause gate oxide breakdown of the devices to which it is applied. Gate oxide breakdown occurs when voltage across the gate alters the molecular structure of the gate oxide to a point where it cannot sufficiently insulate the gate from other components of the device. The breakdown may cause immediate destruction of the device, or it may weaken the oxide enough such that failure may occur early in the operating life of the device and thereby cause later device failure in the field.
In MOS integrated circuits, the inputs are typically connected to operate the gate of one or more MOS transistors. Additionally, all pins are provided with protective circuits to prevent excessive voltages from damaging the MOS gates. These protective circuits, which are usually placed between the input and output pads on a chip and the transistor gates to which the pads are connected, are designed to begin conducting, or to undergo breakdown, thereby providing an electrical path to ground when excess voltage occurs. Such protection devices are designed to avalanche (passing a large amount of current, and dissipating the energy of the incoming transient) before the voltage on the input pin can reach levels that would damage the gate oxide. Because the breakdown mechanism is designed to be nondestructive, the protective circuits provide a normally open path that closes only when the high voltage appears at the input or output terminals, harmlessly discharging the device to which it is connected.
A CDM clamp is commonly used to protect devices from high voltage spikes where a pin is connected to a MOS gate. The CDM clamp serves to hold or “clamp” high voltage from an electrostatic discharge, for example, until it can be safely dissipated through protective circuitry. The CDM clamp connects an N-type diffusion region to the pin. A guardring around the CDM clamp, consequently, must be used to prevent latch-up caused by the pin subjected to a voltage below ground. “Latch-up” is the self-sustaining current flow through the device that results when high voltage from the electrostatic discharge activates a normally closed electrical path through the device.
To effectively prevent damage from large voltages, however, the guardring must be relatively large and surround the CDM clamp. Not only does a large guardring consume valuable space within the device, surrounding the CDM clamp with the large guardring forces greater distance between the clamp and the protected device, which reduces the protection afforded to the device. What is needed is a CDM clamp that better protects delicate circuitry from electrostatic discharge and consumes less device area than currently available CDM clamps.